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SNAD01B 8-channel 8-bit adc ======== contents ======== 1. gene r a l d e sc r i pti o n ............................................................................................................ ........................... 3 2. feat u r es ....................................................................................................................... ............................................. 3 3. ap pli c atio ns ................................................................................................................... ....................................... 3 4. bloc k d i a g r a m .................................................................................................................. ................................... 4 5. pi n as si g n me nt ................................................................................................................. ..................................... 4 6. fu n c ti o n a l de s c ript i o n s ........................................................................................................ ..................... 5 i nterface f ormat ............................................................................................................................... .............................. 5 c hannel s et ti ng ............................................................................................................................... ................................ 7 c ontrol r egi s ter s etting ............................................................................................................................... ............... 7 ad c r ead t im i n g ............................................................................................................................... ............................... 8 t iming of d igi t al i nput r ea ding ............................................................................................................................... .... 9 p ower d own & c hannel w ake -u p ............................................................................................................................. 10 b andgap refe rence ............................................................................................................................... ......................... 11 i nput c hanne l pa d (c hann el 0~6) ........................................................................................................................... .1 2 b attery m oni toring (c hannel 7 only ) .................................................................................................................... 13 7. elect r i cal charac t e ri sti c s ..................................................................................................... ............. 14 8. ap pli c atio n c i r c u it s ........................................................................................................... .......................... 15 e xample c irc u it : snad0 1 b wor k s wit h s onix 4- bit s eri e s c ontroll e r .......................................................... 15 9. e x a m ple p r o g r am s : .............................................................................................................. .......................... 16 p rogram 1: s et c onfigurat ion of sna d 0 1b .......................................................................................................... 27 p rogram 2: r ead adc result from c han nel 1 ...................................................................................................... 27 p rogram 3: r ead d igital i n p ut data from c h 4, c h 3, c h 2 .................................................................................. 28 p rogram 4: p owe r - down sna d 01b and h ost , and w ak e - up .............................................................................. 28 p rogram 5: b attery l ow d etection ......................................................................................................................... 29 10. pa d d i ag r a m .................................................................................................................... ............... 30 version: 1.3 july 31, 2003 1
SNAD01B 8-channel 8-bit adc amendment history v e r s i o n d a t e d e s c r i p t i o n ver 1.1 february 12, 2003 first issue. ver 1.3 july 31, 2003 1. add the version code ?b? of chip no. 2. this spec is modified form snad01_v1.3 3. add standby current more than 50 ua in page 10 note: this docum ent is used to identify the different version ?b? & ?c? of snad01, the most important is standby current and power down setting between version ?b? & ?c?. for the detail please refer to related section. version: 1.3 july 31, 2003 2
SNAD01B 8-channel 8-bit adc 1. general description SNAD01B is a low cost seria l 8- bit s a dc with 8 in dividua l inpu t cha nne ls. e a ch cha nne l can be ind epen d ently pro g ra mmed to a d i git a l o r ana log inp u t mo de. in the a nalog inp u t mode, this sing le- ended chan nel accepts an a nalog in put sign al fr om 0 to v ref and co n v erts the sig nal into 12- bit d i gital code s (w ith 8-bit a ccur a cy guaran teed ). in the dig i t a l inpu t mod e , th e chan n e l can be treated a s digita l inpu t po rt an d the lo g i c leve l a ppe ars at the ch annel can be acquir ed. s n ad01b has a syn c hr onous 3-wire s ser i al inter f ace. th roug h this inte rfa c e, the host cpu can ea sily contro l SNAD01B. during a-to - d conversion , the typical current con s u m ption is 50 0ua at 25 khz throu ghpu t -rate and +3v pow er supply. s n ad01b includes a powe r-down mode , which r edu ces maximum curr ent consumption to less than 1ua. the r e fere nce volta g e ca n be varie d between 1v and +v cc , pr oviding a cor r espo nding input voltage r ang e of 0v to v re f . SNAD01B also has a n on-chip 1.1 7 v bandg ap referen c e t h at can be utilized for consta nt vo lta ge input (e specially fo r b a ttery monit o ring ap plica t ion s ). th e bandga p reference circuitry consumes 300 2. fea t ures ? ? ? ? ? ? ? 3. applica t ions ? ? ? ? ? ? version: 1.3 july 31, 2003 3
SNAD01B 8-channel 8-bit adc digital input bus extender ? 4. block diagram 8-channels analog/digital input mux 8-bit sar adc serial interface and control logic vrh start clk dio avdd vddd avss vssd ch0/di0 ch1/di1 ch2/di2 ch3/di3 ch4/di4 ch5/di5 ch6/di6 ch7(bat)/di7 1.2v bandgap reference figure1 block diagram of adc. 5. pin assignment pin name i/o description ch[7] ~ ch[0] i analog input / digital input ref i reference voltage of analog signal vdd i positive power vss i negative power avdd i positive power of analog circuit avss i negative power of analog circuit start i command initialization signal (from host controller) clk i clock of data communication and ad conversion (from host controller) dio io data input and output of data communication version: 1.3 july 31, 2003 4
SNAD01B 8-channel 8-bit adc 6. functional descriptions host cpu output port1 output port2 i/o port snad01 start clk dio start clk dio vdd avdd ref vdd ` vss avss ch[0] ch[1] ch[7] analog/digital signal 0.1uf figure2 interface with host cpu interface format cm 1 cm 0 id2 id1 id0 cm 2 d6 d5 d7 hi z d3 d2 d4 d0 d1 st ar t cl k dio di[7 ] hi z hi z pd s re a d in g d i gital i npu t r e ading p o we r do wn cm 1 cm 0 cm 2 di[6 ] di[5 ] di4] di[3 ] di[2 ] di[1 ] di[0 ] cm 1 cm 0 cm 2 p o rt inpu t p o rt outpu t p o rt outpu t hi z xxx annel s e tting cm 1 cm 0 cm 2 ch[7 ] ch[6 ] ch[5 ] ch[4 ] ch[3 ] ch[2 ] ch[1 ] ch[0 ] p o rt inpu t p o rt inpu t di[7 ] di[6 ] di[5 ] di4] di[3 ] p o rt inpu t p o rt outpu t xx ~p ds hi z xxx o l r e gister s e tting cm 1 cm 0 cm 2 ph pl rf mb xx xx xx xx p o rt inpu t dio c ontr dio c h dio dio adc figure3 timing diagram of whole commands version: 1.3 july 31, 2003 5
SNAD01B 8-channel 8-bit adc 1. dio is hiz while start is high. 2. the interface logic begins to interpret a command at the falling edge of the start signal. 3. the command id (sent by host) is received in the first three clock cycles from dio. 4. the o perat io ns includ e c hanne l sett in g, adc rea d ing, dig i ta l i nput re adin g and power down. 5. dio becomes to hiz while start returns to high. command id operation 000 power down (0) 001 channel attribute setting (1:analog, 0:digital) 010 channel wakeup function setting (1:enable, 0:disable) 011 control register setting 1 0 0 a d c c o n v e r s i o n 101 digital input reading 1 1 0 r e s e r v e d 111 power down (1) table1 command description table 1. 000/111: adc enters into power down after receiving this command. 2. 001: se t th e attrib ute each ch anne l t o be an ana log or a digita l input w i th the seq uen ce o f channel 7 to 0. (1:analog; 0:digital) 3. 010: set the wakeup fun c tion of ea ch channe l to be enabled or disabled with t he se quen ce of channel 7 to 0. (1:enable; 0:disable) 4. 011: setting the values of control registers. 5. 100: adc st arts to convert t h e ana lo g sign al of t he select ed chann el aft e r re ceivin g this command. 6. 101: adc st arts to read t he d i gital in p u t of every channe l with t he seque nce of cha nnel 7 to 0. 7. 110: adc enters into testing mode. version: 1.3 july 31, 2003 6
SNAD01B 8-channel 8-bit adc channel setting figure3 the timing diagram of channel attribute/wakeup setting st ar t cl k hi z di o 0/1 1/0 0/0 ch [ 7 ] ch [ 6 ] ch [ 5 ] ch [ 4 ] ch [ 3 ] ch [ 2 ] ch [ 1 ] ch [ 0 ] xxx p o r t input command 001: channel attribute setting. command 010: wakeup function setting. in attribute settin g , ?1? means an alo g and ?0? means digit a l. i n wakeup se tting , ?1? means enable and ? 0 ? means disable. aft e r a ll of t he ch an nels are set, the dio port remains inpu t mode and all the following data are ignored. control register setting st ar t clk hi z dio 1 1 0 ph pl rf mb xx x p o rt inp u t xx x xx x xx x xx x figure4 the timing diagram of control registers setting 1. command id: (011) 2. 4-bit dat a b e h ind comma nd id are lo a ded into cont rol r egister s with t he seq uence of ph, pl, rf and mb. 3. the function of each control registers are as table2. version: 1.3 july 31, 2003 7
SNAD01B 8-channel 8-bit adc n a m e f u n c t i o n ph set the pu ll- up re sistor of the ch an nel in d i g i ta l inpu t mode . 1:on, 0:off. pl set the pu ll- down resist o r of the ch a nnel in dig i ta l inpu t mode . 1:on, 0:off. rf set the bandgap reference. 1:on, 0:off. mb for test ing chip on ly, alw a ys set mb=0 in system power-on init ializa tio n routine. table2 the function table of control registers note: 1. the condition of both ph=1 and pl=1 is prohibited. 2. pull-up an d pull-down r e sistor s ar e not a c ti vate d while the co rrespo nding chann el is se t as analog input m ode. adc read timing 0 0 id2 id1 id0 1 hi z d7 d6 d4 d3 d5 d1 d0 d2 st ar t cl k dio p o r t input p o r t output xx t ac q xx pd s figure5 the timing diagram of adc reading 1. command id: (100) 2. 3-bit channel number data behind command id. 3. the ana log sign al o f the sele cte d ch a nnel is samp led to adc. adc refers t he refer ence voltage and convert s t he samp led analog sig nal t o d i git a l doma i n by successive- approximation method. 4. the 8-b i t out put da ta (r esult o f conver sion ) of adc is sen t to di o port from msb and is trigg e red by clk. the m a ximum clock fre quen cy is 50 0khz @ 2.7v. (maximum conversion rate=25khz) version: 1.3 july 31, 2003 8
SNAD01B 8-channel 8-bit adc 5. after the 8-bits adc data has be en se nt out, if t he start is ke pt in low a n d clk is kep t in hig h /low t r ansitio n, th e n the d a ta with un certa i n value are ke pt app earing on dio. the s e data can just be ignored. channel id[2:0] selected channel 0 0 0 c h 0 0 0 1 c h 1 0 1 0 c h 2 0 1 1 c h 3 1 0 0 c h 4 1 0 1 c h 5 1 1 0 c h 6 1 1 1 c h 7 table3 channel selection table. timing of digital input reading st ar t cl k d i[7] hi z di o 0 1 1 d i[6] d i[5] di 4 ] d i[3] d i[2] d i[1] d i[0] d i[7] d i[6] d i[5] di 4 ] d i[3] d i[2] d i[1] d i[0] d i[7] p o rt i nput p o r t o u tput figure6 the timing diagram of the digital input reading 1. command id: (101). 2. the digita l d a ta of ea ch channe l is sen t to the dio p o rt with t he sequen ce of channe l 7 to 0 . 3. after a ll of t he channe ls are r ead, if t he start is ke pt in low and c l k is kept in high/low transitio n, t h e dig i ta l dat a of ea ch chan nel is sent to the dio por t again wit h t h e sequence of channel 7 to 0 cyclically. 4. pulling start to high terminates this digital input reading. note: on ce a chann el is programm ed as a nalog ty pe, the co rre spond ing d a t a is ?0? in d i g i tal input reading com m and. version: 1.3 july 31, 2003 9
SNAD01B 8-channel 8-bit adc pow e r dow n & channel wake-up 00 0 11 1 snad01 enters into power-down mode start clk dio dio figure7 the timing diagram of power down command start clk ch n ch n dio dio wake-up host cpu hiz hiz wake-up procedure ending figure8 the timing diagram of power down command 1. the powe r d o wn comma nd (00 0 /11 1 ) is se nt t o s n ad01b in t he first thre e cycles, and then SNAD01B enter s int o power do wn mode at the 5 th clock cycle, con s u m ing almost no current (less than 1ua). 2. after SNAD01B enter s po wer down (mode 0: command 000), SNAD01B sends ? 0 ? out to dio until a valid log i c tra n s it ion ap pear s on any wakeup- enab le d digital input channe l. once the tran sitio n occu rs, sn ad01b toggles dio to ?1 ? to inf o rm host contro ller . after re ceiving ?1? fr om dio, ho st co ntro ller shou ld t u rn start back t o ?1 ? t o inform sn ad01b tha t the power-down stage is over . otherwise, SNAD01B keeps send in g out ?1? to d i o and does not recognize any other transitions on any channels. version: 1.3 july 31, 2003 10
SNAD01B 8-channel 8-bit adc 3. after SNAD01B enter s po wer down (mode 1: command 111), SNAD01B sends ? 1 ? out to dio until a valid log i c tra n s it ion ap pear s on any wakeup- enab le d digital input channe l. once the tran sitio n occu rs, sn ad01b toggles dio to ?0 ? to inf o rm host contro ller . after re ceiving ?0? fr om dio, ho st co ntro ller shou ld t u rn start back t o ?1 ? t o inform sn ad01b tha t the power-down stage is over . otherwise, SNAD01B keeps send in g out ?1? to d i o and does not recognize any other transitions any the channels. 4. the clk may stop bu t s t art oug ht to remain at low level in the who l e power d o wn mode. note: 1. wake up f unct i on is o n ly d edicate d to the cha nnel wh ich is dig i ta l inp u t type and wakeup-enabled. 2. in SNAD01B ver s io n, the sta ndb y curr ent will m o re than 50ua in a d conve r sio n reference voltage use ?ref? pin connected external voltage. bandgap reference figure8 circuit diagram of adc bandgap reference selection vdd vss ref pad to r e ferenc e hi gh of the a d c rf rf + r f m b 1.2v ban dgap r e fe rence on chip o f f ch ip if t he int e rna l ban dgap re f e rence is tur ned on (rf=1), the refe r ence volt age of adc is supp lie d by output volt age of the interna l ba nd gap ref e ren c e circuit . t h is bandg ap consumes a bout 300 a. the ou tpu t volt age of bandga p r e f e rence is ar ound 1.1 7 v typically. note: mb fo r ch ip test o n ly. alwa ys se t mb=0 wit h comm and (011) in s yst e m power-on initialization routine. version: 1.3 july 31, 2003 11
SNAD01B 8-channel 8-bit adc input channel pad (channel 0~6) vdd vss ench[x] to adc di[x] ch[x] ench[x] pull-high resistor pull-low resistor ench[x]: 1: analog in / 0: digital in ph&ench[x] pl&ench[x] figure9 circuit diagram of the input channel pad 1. if a cha nne l is progr ammed to ana log input mode , then the cor r espo nding interna l signa l, ench[x],=1. as in figure9, pull- high and pull-low are di sabled. and the path to digital input is blocked. all digital reading operation of this channel will get the result ?0?. 2. if a chann el is prog rammed to d i gital input mode, t hen the cor r e spon din g in terna l signa l , ench[x],=0. as in figure9, the path to adc is removed. 3. while in d i git a l input mod e , th is inp u t port c an be config ured to be float ing, weak pull up , or pull down by sett ing t he contro l reg i st e r ph and pl as figure 9 , where ph&pl=1 is for b id den. the weak pull resistance is about 500k ? @3v. 4. the d e fau l t status (d igital/ analo g , pull u p /down) of th e ch anne ls a r e not de fin e d aft e r p o wer on, so initialization of each channel to define a correct state should be done. 5. mode of each channel (ench[x]) can be set by command 001. version: 1.3 july 31, 2003 12
SNAD01B 8-channel 8-bit adc battery monitoring (channel 7 only ) ench[7] to adc di[7] vss 20k 10k 30k vss battery ench[7] vdd vss ch[7] ph&ench[x] pl&ench[x] figure10 the circuit of the input pad of channel 7 1. while rea d a dc command is sent and cha nne l 7 is sele cte d , ad c can be used to monito r the battery voltage. 2. the circuit of battery voltage monitoring is shown in battery monitoring (channel7 only) 3. the bat tery voltag e is six times adc measur ing vo lt age. t hus, t he measur ed resu lt e qua ls to 1/6*battery voltage. 4. while chan n e l 7 is set to t he a nalog in put mode , an in put resisto r (60 k ? ) exists from ch[7 ] to vss. to save unnecessary power consumpti on, ch[7] should be switch to digital input type when ch[7] is not measured. not e : ch[7] i s different f r om the ot he r 7 ch an nel s. th e i n p u t volta ge i s re du ce d to 1/ 6 bef ore it i s sent into adc. version: 1.3 july 31, 2003 13
SNAD01B 8-channel 8-bit adc 7. electrical characteristics typical values apply for v dd =v ref =3.0 v, t amb =25 sy m b o l p a r a m e t e r m i n ty p m a x uni t conditions analog-to-digital converter v dd o p e r a t i n g v o l t a g e 2 . 7 3 . 0 5 . 2 5 v i dd o p e r a t i n g c u r r e n t 4 0 0 6 5 0 ? version: 1.3 july 31, 2003 14
SNAD01B 8-channel 8-bit adc 8. applica t ion circuits example circuit: SNAD01B w o rks w i th sonix 4-bit series controller ch[0], ch[1], ch[2]: analog input ch[6]: digital input ch[7]: battery voltage detect ref=vdd+ 4-bit voice chip p22 snad01 start clk dio vdd avdd ref vdd ` vss avss ch[0] ch[1] ch[7] analog signal 0.1u f vdd p21 p20 vss sn300/500 sn65/66/67/68/6a analog signal ch[2] analog signal ch[6] vdd figure11 SNAD01B works with sonix 4-bit series controller version: 1.3 july 31, 2003 15
SNAD01B 8-channel 8-bit adc 9. example programs: host controller: snc500. app licati on circuit is identical to figure11. p22: start. p21: clk. p20: dio. macro programs: (def.h) i p2state equ m0 port_l equ m1 port_h equ m2 ad_out_l equ m3 ad_out_h equ m4 tmp equ m5 tmp1 equ m6 ;;******************************** @on_st art macro ;;set st art = 0 mov a #1011b and a p2state mov p2state a mov p2 a endm ;;******************************** @off_st art macro ;;set st art = 1 mov a #0100b or a p2state mov p2state a mov p2 a endm ;;******************************** @clock macro mov a #0010b ;;set clk l ? h and h ? l or a p2state mov p2 a mov a #1101b and a p2state mov p2state a mov p2 a endm ;;******************************** @send_0 macro mov a #1110b ;;host send 0 ? dio and a p2state version: 1.3 july 31, 2003 16
SNAD01B 8-channel 8-bit adc mov p2state a mov p2 a endm ;;******************************** @send_1 macro mov a #0001b ;;host send 1 ? dio or a p2state mov p2state a mov p2 a endm ;;******************************** @send macro data ; ;host send 1-bit const a nt (#1 or #0) ? dio mov tmp data mov a #1110b and a p2state or a tmp mov p2state a mov p2 a endm ;;******************************** @read_dio macro ;;read dio ? a.0 (1-bit ) mov a p2 mov tmp #0001b and a tmp endm ;;******************************** @p20_out_mode macro ; ;swit ch all 4-bit of p2 t o out p ut mode mov a #0000b mov p2s a endm ;;******************************** @p20_in_mode macro ; ;swit ch p2.0 (dio) t o input mode mov a #0001b mov p2s a mov a #1110b and a p2state mov p2state a mov p2 a endm version: 1.3 july 31, 2003 17
SNAD01B 8-channel 8-bit adc ;;************************************************************************** ;; set analog/digital mode to each channel (1:analog, 0:digital) * ;; y 7 ? ch7. y 6 ? ch6. y 5 ? ch5, ? * ;;************************************************************************** @set_attrib macro y 7 ,y 6,y 5 ,y 4,y 3 ,y 2,y 1 ,y 0 @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (001) @clock @send_0 @clock @send_1 @clock @send y 7 ;; send y 7 t o y 0 @clock @send y 6 @clock @send y 5 @clock @send y 4 @clock @send y 3 @clock @send y 2 @clock @send y 1 @clock @send y 0 @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm ;;************************************************************************* ;; set w a keup function enable/disable (1:enable, 0:disable) * ;; y 7 ? ch7. y 6 ? ch6. y 5 ? ch5, ? * ;;************************************************************************* @set_w akeup macro y 7 ,y 6,y 5 ,y 4,y 3 ,y 2,y 1 ,y 0 @p20_out_mode ;; swit ch p2 t o out p ut mode version: 1.3 july 31, 2003 18
SNAD01B 8-channel 8-bit adc @on_st art ;; set st art = 0 @s end_0 ;; send command (010) @clock @send_1 @clock @send_0 @clock @send y 7 ;; send y 7 t o y 0 @clock @send y 6 @clock @send y 5 @clock @send y 4 @clock @send y 3 @clock @send y 2 @clock @send y 1 @clock @send y 0 @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm ;;********************************************************************** ;; setup control register * ;; ph: pull-high register. pl:pull-low register. * ;; rf: bandgap reference enable * ; ; m b : s e t 0 a l w a y s * ;;********************************************************************** @set_control_reg macro ph,pl,rf,mb @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (011) @clock @send_1 version: 1.3 july 31, 2003 19
SNAD01B 8-channel 8-bit adc @clock @send_1 @clock @send ph ;; send ph, pl, rf, mb @clock @send pl @clock @send rf @clock @send mb @clock @off_st art ;; set st art = 1 @p20_in_mode ;; swit ch p2.0 t o input mode endm ;;******************************************************************* ;; let SNAD01B enter pow e r-dow n mode 0 * ;;******************************************************************* @pow er_dow n_0 macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_0 ;; send command (000) @clock @send_0 @clock @send_0 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock @clock @clock @clock @clock ;; SNAD01B ent e rs power-down at t h e 8-th clock edge. endm version: 1.3 july 31, 2003 20
SNAD01B 8-channel 8-bit adc ;;***************************************************************** ;; let SNAD01B enter pow e r-dow n mode 1 * ;;***************************************************************** @pow er_dow n_1 macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_1 ;; send command (111) @clock @send_1 @clock @send_1 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock @clock @clock @clock @clock ;; SNAD01B ent e rs power-down at t h e 8-th clock edge. endm ;;***************************************************************** ;; read adc from channel n (n= n2,n1,n0) * ;; e.g.: ch 5 (n2, n1, n0= #1, #0, #1 * ;; 8-bit data ? (ad_out_h, ad_out_l) * ;;***************************************************************** @read_adc macro n0, n1, n2 @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @send_1 ;; send command (100) @clock @send_0 @clock @send_0 @clock @send n2 ;; send channel number @clock @send n1 @clock version: 1.3 july 31, 2003 21
SNAD01B 8-channel 8-bit adc @send n0 @clock @p20_in_mode ;; swit ch p2.0 t o input mode @clock ;; wait for 2 more clocks @clock mov ad_out_l #0 mov ad_out_h #0 ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_h.3 mov tmp1 #1000b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_h.2 mov tmp1 #0100b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_h.1 mov tmp1 #0010b @read_dio caje #0 @f mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @clock ; ; read dio and save 1-bit dat a in ad_out_h.0 mov tmp1 #0001b @read_dio caje #0 @f version: 1.3 july 31, 2003 22
SNAD01B 8-channel 8-bit adc mov a ad_out_h or a tmp1 mov ad_out_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_l.3 mov tmp1 #1000b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_l.2 mov tmp1 #0100b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in ad_out_l.1 mov tmp1 #0010b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** @clock ; ; read dio and save 1-bit dat a in ad_out_l.0 mov tmp1 #0001b @read_dio caje #0 @f mov a ad_out_l or a tmp1 mov ad_out_l a @@: ;;*************************************** version: 1.3 july 31, 2003 23
SNAD01B 8-channel 8-bit adc @clock @off_st art ;; set st art = 1 endm ;;***************************************************************** ;; read digital input: * ;; 8-bit data ? (port_h, port_l) * ;;***************************************************************** @read_port macro @p20_out_mode ;; swit ch p2 t o out p ut mode @on_st art ;; set st art = 0 @s end_1 ;; set command (101) @clock @send_0 @clock @send_1 @clock @p20_in_mode ;; swit ch p2.0 t o input mode mov port_l #0 mov port_h #0 ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.3 mov tmp1 #1000b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.2 mov tmp1 #0100b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a version: 1.3 july 31, 2003 24
SNAD01B 8-channel 8-bit adc @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.1 mov tmp1 #0010b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_h.0 mov tmp1 #0001b @read_dio caje #0 @f mov a port_h or a tmp1 mov port_h a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.3 mov tmp1 #1000b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.2 mov tmp1 #0100b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.1 mov tmp1 #0010b @read_dio version: 1.3 july 31, 2003 25
SNAD01B 8-channel 8-bit adc caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock ;; read dio and save 1-bit dat a in port_l.0 mov tmp1 #0001b @read_dio caje #0 @f mov a port_l or a tmp1 mov port_l a @@: ;;*************************************** @clock @off_st art ;; set st art = 1 endm ;;*************************************** version: 1.3 july 31, 2003 26
SNAD01B 8-channel 8-bit adc program 1: set configuration of SNAD01B ;; setup configuration of SNAD01B ;; ;; with pull-low, bandgap on. (ph=0, pl=1, rf=0,mb=0) ;; ;; ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 ;; analog/digital: b a a d d d a a :b, battery detect ;; wakeup: x x x no yes yes x x ;; snc520 program include def.h start: mov a #1111b mov p2s a mov a #0000b mov p2 a mov p2state #0 @set_control_reg #0, #1, #0, #0 ;; set control registers program 2: read adc result from channel 1 ;; inherit from program 1 ;; 8-bit adc result of channel 1 in ( ad_out_h, ad_out_l) @read_adc #0, #0, #1 ;;get adc result from ch1 in ( ad_out_h, ad_out_l) ? ? version: 1.3 july 31, 2003 27
SNAD01B 8-channel 8-bit adc program 3: read digital input data from ch4, ch3, ch2 ;; inherit from program 1 ;; after reading, ;; port_h.0 = input of ch4 ;; port_l.3 = input of ch3 ;; port_l.2 = input of ch2 @read_port ;;get adc result in ( ad_out_h, ad_out_l) ? ? program 4: pow e r-dow n SNAD01B and host, and wake-up ;; inherit from program 1 ;; enter power-down mode (0) @power_down_0 ;;SNAD01B enters power-down mode (0) end ;; host (snc520) enter power-down ? ? trigger: @off_start ;; set start=1 ? @read_port ;; read trigger condition or debounce procedure starting from here ? ? version: 1.3 july 31, 2003 28
SNAD01B 8-channel 8-bit adc program 5: battery low detection snc520 SNAD01B start clk dio vdd avdd ref vss avss ch[7] vdd 0.1uf vdd vdd vdd vss p20 p21 p22 vdd battery: 1.5vx3 an application uses three 1.5v batteries for power supply. during operation, the power of batteries keeps consumed and the voltage of battery keeps going down. now, voltage lower than 3.6v is treated as ?battery low?. the adc and bandgap reference circuit in SNAD01B can be utilized to detect ?battery low?. the voltage through channel 7 to a dc is r educed to 1/6*vdd (fi gure10). thus, when vdd=3.6v, the voltage into adc is around 0.6v. and bandgap is chosen for reference voltage (approximately 1.17v wit hin the whole operation voltage range). the value acquired from adc is about (0.6/1.17)*256=131. for simplification consideration, we choose ?adc?s readout < 128? as ?battery low? condition. ;; inherit from program 1 ;; enter power-down mode (0) checkbattery: @set_control_reg #0, #1, #1, #0 ;; set rf=1, turn-on bandgap @set_attrib #1, #1, #1, #0, #0, #0, #1, #1 ;; switch ch7 to analog mov m15 #0 checkagain: @read_adc #1, #1, #1 ;; read ch7 mov a #1000b and a ad_out_h caje #1000b b a t t e r y _ l o w _ n o ;; if (value>=128) then not battery low mov a m15 inca mov m15 a caje # 3 b a t t e r y _ l o w _ y e s ;; if (value<128) for 3 times, then jmp checkagain ;; battery low. battery_low_yes: mov m14 #1 version: 1.3 july 31, 2003 29
SNAD01B 8-channel 8-bit adc battery_low_no: @set_control_reg #0, #1, #0, #0 ;; set rf=0, turn-off bandgap @set_attrib #0, #1, #1, #0, #0, #0, #1, #1 ;; switch ch7 to digital ;; to save operating current 10. p ad diagram dice form no pad name x ( um) y(um) no pad name x ( um) y(um) 1 c h 0 - 6 2 3 . 5 0 3 5 2 . 5 0 9 v s s 6 2 3 . 5 0 - 4 1 7 . 5 0 2 c h 1 - 6 2 3 . 5 0 2 4 2 . 5 0 1 0 v d d 6 2 3 . 5 0 - 3 0 7 . 5 0 3 c h 2 - 6 2 3 . 5 0 1 3 2 . 5 0 1 1 d i o 6 2 3 . 5 0 - 1 9 7 . 5 0 4 c h 3 - 6 2 3 . 5 0 2 2 . 5 0 1 2 c l k 6 2 3 . 5 0 - 8 7 . 5 0 5 c h 4 - 6 2 3 . 5 0 - 8 7 . 5 0 1 3 s t a r t 6 2 3 . 5 0 2 2 . 5 0 6 c h 5 - 6 2 3 . 5 0 - 1 9 7 . 5 0 1 4 a v d d 6 2 3 . 5 0 1 3 2 . 5 0 7 c h 6 - 6 2 3 . 5 0 - 3 0 7 . 5 0 1 5 v s s 6 2 3 . 5 0 2 4 2 . 5 0 8 c h 7 - 6 2 3 . 5 0 - 4 1 7 . 5 0 1 6 r e f 6 2 3 . 5 0 3 5 2 . 5 0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 1 2 10 vdd 11 dio 12 clk start 13 14 avdd 15 avss 16 ref 9 vss 3 4 5 6 7 8 (0,0) chip size=1350 x 950um SNAD01B note: the substrate must be c onnected to vss in pcb layout version: 1.3 july 31, 2003 30
SNAD01B 8-channel 8-bit adc version: 1.3 july 31, 2003 31 disclaimer the information appearing in sonix web pages (?this publicat ion?) is believed to be accurate. however, this publication could contain technical inaccuracies or typographical errors. the reader should not assume that this publication is e rror-free or that it will be suitable for any particular purpose. sonix makes no warr anty, express, statut ory implied or by description in this publication or other documents which are refe renced by or linked to this publication. in no event shall sonix be liabl e for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. this publication was developed for products offe red in taiwan. sonix may not offer the products discussed in this document in other c ountries. information is subject to change without notice. please contac t sonix or its local repres entative for information on offerings available. integrat ed circuits sold by sonix ar e covered by the warranty and patent indemnification provisions sti pulated in the terms of sale only. the application circuits illustrated in this do cument are for refere nce purposes only. sonix disclaims all warranties, including the warranty of merchantability or fitness for any purpo se. sonix reserv es the right to halt production or alter the specifications and prices , and discontinue marketing the products listed at any ti me without notice. accordingly, th e reader is cautioned to verify that the data sheets and othe r information in this publicati on are current before placing orders. products described herein are intended for use in normal commercial applications. applications involving unusual environmental or reliability requirem ents, e.g. military equipment or medical life s upport equipment, are specifically not recommended without additional processing by sonix for such application.

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